chiplab里的icache dcache和cache interface
lsoc1000_mainpipe里的inst_和data_这两个inteface分别和mycpu_top外面的icache dcache通信。
同时icache dcache模块还有接口和core_top里的ram_wrapper通信。
ram_wrapper是cache的实现。
icache和dcache还和cache_interface通信，cache_interface通过AXI协议与core_top外面的axi slave通信获取内存中的数据。
这里内存即可以是通过memory controller取得的ddr内存的数据，也可以是chiplab里用的sram。
core_top外面是soc_top，在chip/soc_demo/sim/soc_top.v里。
这里面的东西在以前的blog里写过了。
soc_top
+—————————————————————————————————————————————————————————————————————————————————————-+ | core_top | | | | | | +————————————————————————————————————————————————————————–+ | | | mycpu_top | | | | | | | | | | | | +——————————————–+ | | | | | icache | | | | | | | | | | | | | | | | | | // icache ram | | | | | | .icache_init_finish | ——————————————————————————————————————————————-+ | | | | | | | | | | | .icache_tag_clk_en_o | | | | | | | .icache_tag_en_o | | | | | | | .icache_tag_wen_o | | | | | | | .icache_tag_addr_o | | | | | | | .icache_tag_wdata_o | | | | | | | .icache_tag_rdata_i | | | | | | | | | | | | | | .icache_lru_clk_en_o | | | | | | | .icache_lru_en_o | | | | | | | .icache_lru_wen_o | | | | | | | .icache_lru_addr_o | | | | | | | .icache_lru_wdata_o | | | | | | | .icache_lru_rdata_i | | | | | | | | | | | | | | .icache_data_clk_en_ \ \ | | \ \ \ .icache_data_en_o | | | | | | | .icache_data_wen_o | | | | | | | .icache_data_addr_o | | | | | | | .icache_data_wdata_o | | | | | | | .icache_data_rdata_i | ———————————————————————————–+ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +——————————–+ | | | | | | | | | lsoc1000_mainpipe cpu | | | | | | | | | | | | | +————————————————–+ | | | | | | | | | ////cpu_control | | cache_interface | | | | | | | | | | //-inst request interface- | | | | | | | | | | .inst_req | | .inst_req | | // icache | | | | | | | | .inst_addr | | .inst_addr .rd_req | | .i_rd_req | | | | | | | | .inst_cancel | | .inst_cancel .rd_addr | | .i_rd_addr | | | | | | | | .inst_addr_ok | | .inst_addr_ok .rd_arcmd | | .i_rd_arcmd | | | | | | | | .inst_rdata | | .inst_rdata .rd_uncache | | .i_rd_uncache | | | | | | | | .inst_valid | | .inst_valid .rd_ready | | .i_rd_ready | | | | | | | | .inst_count | | .inst_count .ret_valid | | .i_ret_valid | | | | | | | | .inst_uncache | | .inst_uncache .ret_last | | .i_ret_last | | | | | | | | .inst_exccode | | .inst_exccode .ret_data | | .i_ret_data | | | | | | | | .inst_exception | | .inst_exception .ret_rstate | | .i_ret_rstate | | | | | | | | | | .ret_rscway | | .i_ret_rscway | | | | | | | | .inst_tlb_req | | .inst_tlb_req | | | | | | | | | | .inst_tlb_vaddr | | .inst_tlb_vaddr .wr_req | | .i_wr_req | | | | | | | | .inst_tlb_cacop | | .inst_tlb_cacop .wr_addr | | .i_wr_addr // axi_control| | | | | | | | | | .wr_data | | .i_wr_data // ar | | | | | | | | | | .wr_awcmd | | .i_wr_awcmd .arid | ————————————————————————————————– | | | | | .wr_awstate | | .i_wr_awstate .araddr | | | | | | | | | | .wr_awdirqid | | .i_wr_awdirqid .arlen | | | | | | | | | | .wr_awscway | | .i_wr_awscway .arsize | | | | | | | | | | .wr_pgcl | | .i_wr_pgcl .arburst | | | | | | | | | | .wr_fmt | | .i_wr_fmt .arlock | | | | | | | | | | .wr_ready | | .i_wr_ready .arcache | | | | | | | | | | | | .arprot | | | | | | | | | | .ex_req | | .i_ex_req .arcmd | | | | | | | | | | .ex_req_op | | .i_ex_req_op .arcpuno | | | | | | | | | | .ex_req_paddr | | .i_ex_req_paddr .arvalid | | | | | | | | | | .ex_req_cpuno | | .i_ex_req_cpuno .arready | | | | | | | | | | .ex_req_pgcl | | .i_ex_req_pgcl //r | | | | | | | | | | .ex_req_dirqid | | .i_ex_req_dirqid .rrequest | | | | | | | | | | .ex_req_recv | | .i_ex_req_recv .rid | | | | | | | | | | | | .rdata | | | | | | | | | | | | .rstate | | | | | | | | | | | | .rscway | | | | | | | | | | | | .rresp | | | | | | | | | | | | .rlast | | | | | | | | | +——————————————–+ | .rvalid | | | | | | | | | | .rready | | | | | | | | | | //aw | | | | | | | | | | .awcmd | | | | | | | | | +——————————————–+ | .awstate | | | | | | | | | | dcache | | .awdirqid | | | | | | | | | | | | .awscway | | | | | | | | | | ////cpu_control | | // dcache .awid | | | | | | | | | | //—-llsc—- .rd_req | | .d_rd_req .awaddr | | | | | | | | .csr_wen | | .csr_wen .rd_addr | | .d_rd_addr .awlen | | | | | | | | .csr_waddr | | .csr_waddr .rd_id | | .d_rd_id .awsize | | | | | | | | .csr_wdata | | .csr_wdata .rd_arcmd | | .d_rd_arcmd .awburst | | | | | | | | .wb_eret | | .wb_eret .rd_uncache | | .d_rd_uncache .awlock | | | | | | | | .llbctl | | .llbctl .rd_arready | | .d_rd_ready .awcache | | | | | | | | | | //data request interface .ret_valid | | .d_ret_valid .awprot | | | | | | | | .pipeline2dcache_bus | | .pipeline2dcache_bus .ret_last | | .d_ret_last .awvalid | | | | | | | | .dcache2pipeline_bus | | .dcache2pipeline_bus .ret_data | | .d_ret_data .awready | | | | | | | | | | .ret_data_id | | .d_ret_rid //w | | | | | | | | | | .ret_rstate | | .d_ret_rstate .wid | | | | | | | | | | .ret_rscway | | .d_ret_rscway .wdata | | | | | | | | | | | | .wstrb | | | | | | | | | | .wr_req | | .d_wr_req .wlast | | | | | | | | | | .wr_addr | | .d_wr_addr .wvalid | | | | | | | | | | .wr_data | | .d_wr_data .wready | | | | | | | | | | .wr_awcmd | | .d_wr_awcmd //b | | | | | | | | | | .wr_awstate | | .d_wr_awstate .bid | | | | | | | | | | .wr_awdirqid | | .d_wr_awdirqid .bresp | | | | | | | | | | .wr_awscway | | .d_wr_awscway .bvalid | ————————————————————————————————- | | | | | .wr_pgcl | | .d_wr_pgcl .bready | | | | | | | | | | .wr_uc_wstrb | | .d_wr_uc_wstrb | | | | | | | | | | .wr_fmt | | .d_wr_fmt | | | | | | | | | | .wr_ready | | .d_wr_ready | | | | | | | | | | .vic_not_full | | .vic_not_full | | | | | | | | | | .vic_empty | | .vic_empty | | | | | | | | | | | | | | | | | | | | | | .ex_req | | .d_ex_req | | | | | | | | | | .ex_req_op | | .d_ex_req_op | | | | | | | | | | .ex_req_paddr | | .d_ex_req_paddr | | | | | | | | | | .ex_req_cpuno | | .d_ex_req_cpuno | | | | | | | | | | .ex_req_pgcl | | .d_ex_req_pgcl | | | | | | | | | | .ex_req_dirqid | | .d_ex_req_dirqid | | | | | | | | | | .ex_req_recv | | .d_ex_req_recv | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +————————————————–+ | | | | | | | | | | | | | | | | +——————————– | | | | | | | | | | | | | | | | | | | | | | | | | // dcache ram | | | | | | | | .dcache_init_finish | | +————————————————————–+ | | | | | ——————————————————————————– | ram_wrapper u_ram_wrapper | | | | | .dcache_tag_clk_en_o | | | | | | | | .dcache_tag_en_o | | | | | | | | .dcache_tag_wen_o | | | | | | | | .dcache_tag_addr_o | | | | | | | | .dcache_tag_wdata_o | | | | | | | | .dcache_tag_rdata_i | | | | | | | | | | | | | | | | .dcache_lrud_clk_en_o | | | | | | | | .dcache_lrud_en_o | | | | | | | | .dcache_lrud_wen_o | | | | | | | | .dcache_lrud_addr_o | | | | | | | | .dcache_lrud_wdata_o | | | | | | | | .dcache_lrud_rdata_i | | | | | | | | | | | | | | | | .dcache_data_en_o | | | | | | | | .dcache_data_clk_en_o | | | | | | | | .dcache_data_wen_bank0_o | | | | | | | | .dcache_data_wen_bank1_o | | | | | | | | .dcache_data_wen_bank2_o | | | | | | | | .dcache_data_wen_bank3_o | | | | | | | | .dcache_data_wen_bank4_o | | | | | | | | .dcache_data_wen_bank5_o | | | | | | | | .dcache_data_wen_bank6_o | | | | | | | | .dcache_data_wen_bank7_o | | | | | | | | .dcache_data_addr_o | | | | | | | | .dcache_data_wdata_o | | | | | | | | .dcache_data_rdata_i | ——————————————————————————– | | | | | | | | | | | | | +——————————————–+ | | | | | | | | | | | | | | | | | | | +————————————————————–+ | | | | | | | | | | +————————————————————————————————————————————————————————–+ | | | +—————————————————————————————————————————————————————————————————————————————————————-+
图画的太大了，显示不出来，只有截图了。
