记点和icache相关的
Line Fill Buffer(LFB)
256-bit 4 64-bit
input pfu_icu_req_i,
input [31:3] pfu_icu_addr_i,
input pfu_icu_first_i,
input pfu_icu_priv_i,
input pfu_icu_vf_i,
output icu_pfu_ack_o,
LFB 填充进一个cache line的时候，按总线宽度，可以是4次64-bit。
对外接口的话，icache控制模块icu不需要考虑比如是否是axi burst。
output icu_biu_req,
input biu_icu_ack,
input [63:0] biu_icu_data,
input biu_icu_data_valid,
reg [31:3] lfb_addr;
reg [255:0] lfb_data;
always @(posedge clk or negedge resetn)
if (~resetn) begin
lfb_addr <= {29{1'b0}};
end else if (icu_biu_lf_req & biu_icu_ack) begin
lfb_addr <= fe_addr;
end else if (lfb_data_valid_qual) begin
lfb_addr[4:3] <= lfb_addr[4:3] + 2'b01;
end
// update LFB
always @(posedge clk or negedge resetn)
if (~resetn)
lfb_data[63:0] <= {64{1'b0}};
else if (lfb_data_valid_qual & (lfb_addr[4:3] == 2'b00))
lfb_data[63:0] <= biu_icu_data;
always @(posedge clk or negedge resetn)
if (~resetn)
lfb_data[127:64:0] <= {64{1'b0}};
else if (lfb_data_valid_qual & (lfb_addr[4:3] == 2'b01))
lfb_data[127:64] <= biu_icu_data;
always @(posedge clk or negedge resetn)
if (~resetn)
lfb_data[191:128] <= {64{1'b0}};
else if (lfb_data_valid_qual & (lfb_addr[4:3] == 2'b10))
lfb_data[191:128] <= biu_icu_data;
always @(posedge clk or negedge resetn)
if (~resetn)
lfb_data[255:192] <= {64{1'b0}};
else if (lfb_data_valid_qual & (lfb_addr[4:3] == 2'b11))
lfb_data[255;192 <= biu_icu_data;
biu_icu_data分四次存到lfb_data，每存一次地址加8。
lfb要存到icache里，也就是sram里。这个过程叫allocate，还没搞懂。
cache查询的时候除了在RAM里查，也应该在lfb里找。
lfb大小是不是要和cacheline一个大小？ 看样是不一定。
cortext-m7 lfb 256 bits
cortext-m7 cacheline 128 bits, 2-way,
A single cache line is spread across 4 data RAM lines, each of which stores one dword, 32-bit 这句话英应该是不对的，应该是 a single cache line is spread across 2 data RAM lines, each of which stores 64-bit.
idata_bank_wrap, Each RAM block supports 64-bits of data and 8-bits of ECC information.
itag_bank_wrap, Each RAM block supports 22-bits of data and 7-bits of ECC information.
icache 8KB 16KB?
10 bits tag,
wire [9:0] tag_addr_lu = pfu_icu_addr_qual[14:5];
IDATA_RAM_ADDR_W = 12 IDATA_RAM_W = 72 ITAG_RAM_ADDR_W = 10 ITAG_RAM_W = 29
tag RAM data是22 bits，最高bit [21]表示valid。[20:0]用来和va对比tag。
wire [21:0] tag_wdata_al = {lfb_allocated[0], lfb_addr[31:11]};
wire [9:0] tag_addr_lu = pfu_icu_addr_qual[14:5];
wire [11:0] data_addr_lu_ic1 = {pfu_icu_addr_qual[14:5], pfu_icu_addr_qual[4:3]};
如果LFB hit，把LFB里的一部分64bit传给PFU，PFU接口只接受64bit。
//Forward from the LFB to the PFU
wire [63:0] fe_lfb_data_ic2;
assign fe_lfb_data_ic2 = (fe_addr_ic2[4:3] == 2'b00) ? lfb_data_ic2[63:0] :
(fe_addr_ic2[4:3] == 2'b01) ? lfb_data_ic2[127:64] :
(fe_addr_ic2[4:3] == 2'b10) ? lfb_data_ic2[191:128] :
lfb_data_ic2[255:192];