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chiplab pipeline moudle
ifu里先去掉所有和分支预测有关的信号，只剩下三组信号需要处理。 cpu读取指令的信号 inst_ 后面传回的跳转地址 br_ 给后一级decode的信号，o_port0_ chiplab里是有三个port的，为了简单，ifu只能单发射，虽然接口没有变，但只有port0有效。 NONE0是什么种类的指令？ 在ex1_stage里 wire [`GRLEN-1:0] ex1_none0_result; wire [`GRLEN-1:0] ex1_none1_result; wire ex1_none0_exception; wire ex1_none1_exception; wire [`GRLEN-1:0] ex1_none0_csr_result; wire [`GRLEN-1:0] ex1_none1_csr_result; wire [`GRLEN-1:0] ex1_none0_csr_a; wire [`GRLEN-1:0] ex1_none1_csr_a; 可以看到exception，cache，tlb，csr相关的指令都走NONE。 +-------------------------------------------------------+ | cpu7_ifu_fdp cpu7_ifu | | | | .inst_req | | .inst_addr | | .inst_cancel | | .inst_addr_ok...
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CPU7
The goal is to learn from chiplab project, including how to use verilator to establish a developing and testing framework, how the chiplab cpu’s modules are orgnized, and how to use AXI and ABP bus protocol to connect with memory and peripherial devices. Step 1: Move and rename the chiplab...
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win32k double fetches, case 0 - case 50
case 0 need review DOUBLE FETCH: cr3 0x11ec2f000, syscall 0x1005 user_address 0x3234cfd2f0, user_data 0x80000000, modrm 0xb8, pc 0xfffff960cca34caf user_address 0x3234cfd2f0, user_data 0x80000000, modrm 0x88, pc 0xfffff960cca35035 0x34c30 1267 NtGdiFlushUserBatch Ordinal_1267 XREF[5]: Entry Point(*), 1c02f2ee0(*), NtGdiFlushUserBatch 1c0332a94(*), 1c03663f0(*), 1c037c154(*) 1c0034c30 48 89 5c MOV qword ptr [RSP + local_res8],RBX 24 08...